互联网IT行业职位
Staff Design Engineer 芯片设计
Job Purpose:
- Take the lead role developing micro-architecture, RTL coding and verification for SoC chips.
Key Responsibilities:
- Work with Chip Architect in refining the functional partitioning of the design and its interfaces.
- Develop micro-architecture given the functionality and interfaces required.
- Generate and maintain relevant design and user documentation.
- Implement module in RTL using Verilog and assertions.
- Develop reusable module with verification environments that include models, monitors and checkers. Be responsible for debugging RTL of assigned module.
- Review, document and improve existing module designs as needed.
- Synthesize and optimize RTL code for timing, area, power and testability.
- Assist in developing floor plans and performing full chip integration including 3rd party IPs and memory modules.
- Work with physical design teams for optimizing layout and achieving timing closure on ASIC/SoC designs.
- Incorporate DFT and validate their correct functionality.
- Write test vectors for ATE, verify, and convert them into tester format.
- Participate in testing and debugging silicon.
- Provide strong leadership in making sure design is of highest quality and is executed on time.
Required:
- Minimum BS in EE, MSEE degree preferred with 7+ years of experience in chip design.
- Must have intimate knowledge and experience from RTL to timing verified layout.
- Must have knowledge of Verilog RTL, RTL simulators, synthesis static timing analysis, logic equivalence checker, DFT tools and debugging tools.
- Must have participated in the successful development of complex SoCs, preferably in the consumer electronics space.
- Must be a hands-on designer with proven track record required in utilizing industry standard design tools for verification, synthesis, DFT, and timing closure.
- Must be a team player with excellent communications skills and capable of delivering on time under tight schedule.